QDR II SRAM — 36 Mbit at 250 MHz
It clocks at 250 MHz, delivering two data words per clock cycle on separate read and write ports — effectively doubling throughput versus a single-port SRAM at the same frequency. This part is designed for high-bandwidth applications such as network packet buffers, cache memory in telecom line cards, and high-end test equipment where back-to-back read/write operations cannot tolerate bus-turnaround dead cycles.
The supplier device package is 165-FBGA (13x15). The tray shipping medium is standard for this BGA format.
Lifecycle reality — obsolete, no direct replacement on record
For a BOM that still requires this exact density and QDR II interface, the procurement path is through independent distribution — last-time-buy inventory or verified surplus. If your design can tolerate a different package or density, a parametric search for 36 Mbit QDR II SRAM in a 165-ball BGA may yield a cross, but no pin-compatible alternate is confirmed here.
