36Mbit QDR II SRAM — what the 167 MHz rating buys
The 167 MHz clock rate gives each port a 333 million-transfers-per-second data rate, eliminating the bus-turnaround dead cycles that plague traditional SRAM in back-to-back read-write sequences. The 1.7V to 1.9V core supply aligns with the 1.8V I/O standard common in network processors and FPGAs of that generation.
Housed in a 165-ball FBGA measuring 15x17 mm, the part requires a multilayer PCB with blind vias or microvias to route the dense ball grid. Surface-mount only — no socket option for this package.
New designs should not target this part; existing BOM lines that require it must be filled through the surplus and broker channel.