The Cypress (now Infineon) CY7C1413AV18-250BZC is a 36Mbit synchronous QDR II SRAM organized as 2M x 18 bits, clocked at 250 MHz. The QDR II architecture separates read and write data ports, eliminating bus-turnaround dead cycles — useful when back-to-back read-write throughput is the bottleneck.
At 250 MHz, each of the two independent ports (read and write) can transfer data on every clock edge, giving an effective data rate of 500 million transfers per second per port. For a 36Mbit-wide part, that means the memory controller can keep the pipeline full without inserting idle cycles. If your FPGA or ASIC is already running a 250 MHz memory controller clock, this part matches without needing a PLL ratio or clock-domain crossing.
The 165-ball FBGA measures 15 x 17 mm with a 1.0 mm ball pitch — a standard BGA that a decent hot-air station can rework if you've got a stencil and a preheat plate.