Dual-port SRAM for shared-memory handoff
The CY7C139-25JXC is a 36Kbit dual-port asynchronous SRAM organized as 4K words by 9 bits. Two independent ports with separate address, data, and control lines let two bus masters read or write the same memory array without external arbitration logic.
The 25 ns write cycle time (word, page) matches the read side.
