18Mbit synchronous SRAM for high-throughput data paths
The Infineon CY7C1385D-133AXI is a 18Mbit synchronous SRAM organized as 512K x 36, clocked at 133 MHz with a 6.5 ns access time.
What the 133 MHz clock and 6.5 ns access mean for your bus
The 133 MHz clock rate and 6.5 ns access time set the read-to-data-valid window for the memory controller. At 133 MHz the cycle time is 7.5 ns, so the 6.5 ns access means data appears on the bus just 1 ns before the next clock edge — the controller must capture within that hold window. The 512K x 36 organization gives a 36-bit wide data bus, useful for processor or DSP interfaces that need a full word per cycle without multiplexing.
Infineon lists the CY7C1385D-133AXI as Obsolete. For a BOM already qualified to this footprint and timing, the existing layout and controller settings carry over — no board spin is required if the supply is secured.
Supplied in a 100-TQFP (14x20 mm) tray package, surface-mount. The 0.5 mm pitch demands a controlled impedance layout on the data and address lines, especially at 133 MHz.