133 MHz synchronous SRAM for high-throughput data paths
This is a single-data-rate (SDR) pipeline-burst part, meaning it delivers one 36-bit word per clock cycle after the initial latency. The wide-word organization suits it for high-bandwidth applications like network switch buffers, telecom line-card look-up tables, and military-grade radar signal processing where the data bus width matches the processor or FPGA interface directly.
Military temperature range — rated for extreme environments
The 100-TQFP (14x20 mm) package is surface-mount, so the board assembly process must handle the thermal cycle range; the tray shipping medium is standard for this package size and does not affect the footprint.
Supply voltage and interface — 3.3 V nominal with tight tolerance
The parallel memory interface is common for this class of SRAM; no special termination or series resistors are needed if the trace lengths are kept under 100 mm at 133 MHz. The 6.5 ns access time gives about one clock cycle of read latency, which the memory controller must account for in the bus-turnaround timing budget.