18 Mbit synchronous SRAM — what the 100 MHz clock and 8.5 ns access mean for the bus
The CY7C1381KV33-100AXC is a 18 Mbit synchronous SRAM from Infineon, organized as 512K x 36 bits. The 100 MHz clock and 8.5 ns access time define the read-cycle budget.
Package and footprint — 100-TQFP (14x20 mm)
It is surface-mount only. The tray shipping medium is the standard for this package size.
