18 Mbit synchronous SRAM — 512K x 36, 133 MHz pipeline
The Infineon CY7C1381D-133AXI is a 18 Mbit synchronous SRAM organized 512K x 36, clocked at 133 MHz with a 6.5 ns access time.
Where the 6.5 ns access and 133 MHz clock matter
The 6.5 ns access time defines the first-read latency from address strobe to data valid. At 133 MHz the pipeline delivers a new data word every clock cycle after the initial latency.
Obsolete — sourcing via independent channel
The CY7C1381D-133AXI is listed as obsolete. No direct replacement part number is provided in the available records.