The CY7C1381D-133AXC: For existing BOM lines, this part is sourced through independent distribution channels.
18 Mbit synchronous SRAM — 512K x 36 organization
The CY7C1381D-133AXC is a 18 Mbit synchronous SRAM organized as 512K words by 36 bits. The 36-bit word width maps directly to a 32-bit data bus plus 4 parity or ECC bits — common in networking and telecom line-card buffer applications where parity coverage is needed without an external logic device. The 133 MHz clock frequency and 6.5 ns access time mean the part delivers one 36-bit word per clock cycle in pipelined read mode — a sustained throughput of 4.8 Gbit/s on the parallel bus.
The 100-TQFP is a common pinout for mid-density synchronous SRAMs, which simplifies PCB layout reuse if a second-source part is needed. Supply range is 3.135 V to 3.6 V — a 3.3 V nominal rail with ±5 % margin.