200 MHz synchronous SRAM — 512K x 36 in 100-LQFP
The CY7C1380DV33-200AXI is an 18 Mbit synchronous SRAM organized as 512K words by 36 bits, clocked at 200 MHz with a 3 ns access time from the clock edge.
The laser etch and date-code consistency should be verified against Infineon's marking standards when sourcing from non-franchised stock — the 100-LQFP package is a common target for re-marked parts.
Speed grade and timing margin
The 200 MHz clock frequency and 3 ns access time define the read-to-data-valid window — at 200 MHz the clock period is 5 ns, so the 3 ns access leaves 2 ns for board trace delay and setup at the controller. This is a synchronous SDR (single data rate) architecture — data is captured on the rising clock edge only, which simplifies timing closure compared to DDR variants but halves the theoretical bandwidth per pin.