Memory capacity and bus width — 512K x 36, 18 Mbit
Organised as 512K words by 36 bits, the CY7C1380C-167BZI delivers 18 Mbit of synchronous SRAM. The 36-bit wide data bus suits systems that need a full word plus parity or ECC bits in a single access cycle.
Speed grade — 167 MHz clock, 3.4 ns access
The 3.4 ns access defines the timing closure window for the memory controller.
Package — 165-ball LBGA, 13x15 mm
Housed in a 165-ball LBGA (13x15 mm body), the CY7C1380C-167BZI requires a multi-layer PCB for signal fan-out and decoupling.