The CY7C1373KV33-100AXC is an 18 Mbit synchronous SRAM from Infineon's NoBL (No Bus Latency) family, organized 1M x 18. It clocks at 100 MHz with an 8.5 ns access time, meaning back-to-back reads and writes can happen on consecutive clock cycles without dead cycles on the bus — the NoBL pipeline eliminates the turnaround penalty you'd see on a standard synchronous SRAM. That matters when your controller or FPGA is running a bursty memory access pattern and you can't afford idle cycles between read and write commands.
If your design lives in an unventilated enclosure or sees outdoor exposure, you'll want to look at the industrial-temperature variants in the same family.
Package and footprint — what to tell the layout engineer
It comes in a 100-pin LQFP (also listed as 100-TQFP with a 14x20 mm body). That's a common fine-pitch surface-mount package — 0.5 mm pitch, standard for this density class. The footprint is well-supported in most PCB design libraries. No exposed thermal pad to worry about, but keep the decoupling caps close to the supply pins; at 100 MHz the switching transients need local bypass.
Infineon lists this part as Active. That means no end-of-life notice looming, no last-time-buy scramble.