18 Mbit NoBL synchronous SRAM for high-throughput data buffering
It clocks at 167 MHz with a 3.4 ns access time, eliminating the dead cycle normally required when a read follows a write on a standard synchronous SRAM bus.
167 MHz clock and 3.4 ns access — timing closure for the bus
At 167 MHz the cycle time is about 6 ns, and the 3.4 ns access time leaves roughly 2.6 ns of setup margin before the next clock edge — enough for most FPGA or ASIC interfaces running at this speed class, but the trace-length matching and board impedance need attention. The parallel memory interface means every address and data line is a separate trace; a 100-pin LQFP fanout on a four-layer board is manageable but the 14x20 mm body puts the pins close enough that micro-vias or fine-pitch routing may be needed if the controller sits more than 50 mm away.
NoBL architecture — why it matters for throughput
Standard synchronous SRAMs insert a dead cycle when the bus direction flips from write to read. The NoBL pipeline allows a read command on the clock edge immediately following a write, so the data bus never idles. For a system doing mixed read/write traffic — a packet buffer or a display frame store — this can improve sustained throughput by up to 50% versus a conventional pipelined SRAM at the same clock rate. The trade-off is a slightly more complex controller state machine that must assert the correct command on every rising edge.
No separate VDDQ rail is needed — the I/O and core share the same supply, which simplifies power sequencing.
Active lifecycle — no near-term LTB concern
The base product number CY7C1372 covers multiple speed and temperature variants in the same 100-pin footprint, so if a future design needs a faster or wider part, the pinout stays compatible across the family.