100 MHz NoBL pipeline in a 100-TQFP footprint
The CY7C1371KVE33-100AXI is a 18 Mbit synchronous SRAM from Infineon's NoBL (No Bus Latency) series, organized 512K x 36 and clocked at 100 MHz. The 8.5 ns access time means the first read word appears on the bus within one clock cycle after the address is registered — subsequent reads in a burst pipeline at the full 100 MHz rate with zero dead cycles between transactions. Housed in a 100-lead LQFP (also supplied as 100-TQFP 14x20 mm), this surface-mount package routes 36 data lines plus address and control on a 0.5 mm pitch.
Supply rails and timing margin for the 3.3 V bus
The parallel memory interface uses standard 3.3 V LVTTL levels. Setup and hold times relative to the rising clock edge are specified in the datasheet; the 8.5 ns access time from clock rise to data valid leaves roughly 1.5 ns of margin at 100 MHz for a typical FPGA input register with 1.0 ns setup demand.
Active lifecycle — no end-of-life pressure
Infineon lists the CY7C1371KVE33-100AXI as Active.