18 Mbit synchronous SRAM, 200 MHz pipeline
The CY7C1370KV33-200AXC is a 18 Mbit synchronous SRAM organized as 512K x 36, clocked at 200 MHz with a 3 ns access time from clock rise. It belongs to the NoBL (No Bus Latency) series, which eliminates the dead cycle between read and write transitions on a shared bus — the memory accepts a new address every clock cycle regardless of the previous operation's direction.
Last Buy — sourcing through independent channels
Infineon has classified the CY7C1370KV33-200AXC as Last Buy, meaning the manufacturer's production window is closing and no further orders will be accepted after the final purchase order deadline. For designs already in production, the remaining supply is held in independent distribution and surplus inventory — quantities are lot-specific and confirmed at RFQ time.
3 ns access time — bus timing margin
The 3 ns access time is measured from the rising clock edge to data valid on the output pins, with the output load specified per the datasheet's AC timing conditions. At 200 MHz (5 ns cycle), a 3 ns tCD means the data appears with 2 ns of setup margin to the next clock edge — sufficient for most FPGA I/O banks running at 3.3 V, but the PCB trace delay and output loading must be budgeted into the timing closure.
100-TQFP package and board layout
The device is supplied in a 100-lead TQFP with a 14x20 mm body (EIAJ standard), 0.5 mm pitch — the same footprint as the earlier CY7C1370B series, so a board already laid out for that generation accepts this part without a spin. The commercial temperature grade (0°C to 70°C TA) limits deployment to indoor, temperature-controlled environments — not suitable for extended industrial or automotive ambient ranges.