18 Mbit synchronous SRAM at 167 MHz — the bus-fit decision
The CY7C1370KV25-167BZC: The 36-bit word width maps directly to a 32-bit data bus plus four parity or ECC bits — no byte-lane muxing required at the controller side. Part of Infineon's NoBL™ (No Bus Latency) series, it eliminates the dead cycle between read and write operations that older pipelined SRAMs impose. For a controller that alternates read and write on every clock, that means full 167 MT/s throughput without wait states.
Core supply range is 2.375 V to 2.625 V — a tight 2.5 V nominal rail. The 165-ball FBGA package (13x15 mm body) uses a 1.0 mm ball pitch. Fan-out on a four-layer board is straightforward; a two-layer board will struggle to route the 36 data lines plus address and control without signal-integrity issues at 167 MHz.