NoBL synchronous SRAM at 200 MHz — what the 3 ns access time buys you
The CY7C1370DV25-200BZC: Its 200 MHz clock and 3 ns access time mean back-to-back reads and writes without dead cycles — the NoBL pipeline keeps the data bus fully utilised on every clock edge. That matters for high-throughput applications like network packet buffers, telecom line cards, and DSP scratchpads where a stalled bus costs throughput.
Package: 165-FBGA (13x15 mm)
Cypress lists the CY7C1370DV25-200BZC as Obsolete. That means no further factory orders — no last-time-buy window remains. The only channel is independent distribution: verified surplus, new-old-stock, or broker inventory. For a production BOM, you need to qualify a replacement or secure remaining stock through a trusted independent source. No official Cypress successor is recorded for this exact order code; a pin-compatible drop-in from the same NoBL family may exist, but the buyer should verify fit against the original PCB layout and timing closure.