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Infineon Technologies CY7C1370DV25-167AXCT — Memory (DRAM / SRAM / Flash / EEPROM)

CY7C1370DV25-167AXCT SRAM, 18Mbit, 167 MHz, 100-TQFP

MPNCY7C1370DV25-167AXCT
Obsolete

Infineon Technologies NoBL™ synchronous SRAM, CY7C1370DV25-167AXCT, 18Mbit (512K x 36), 167 MHz clock, 3.4 ns access, 2.375-2.625 V supply, 100-TQFP (14x20 mm), Tape & Reel.

$27.7500Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C1370DV25-167AXCT specifications
ParameterValue
SeriesNoBL™
Memory typeVolatile
MountingSurface Mount
Supply voltage2.375V ~ 2.625V
Clock frequency167 MHz
Memory interfaceParallel
Operating temperature0°C~70°C(TA)
PackageTape & Reel (TR)
TechnologySRAM - Synchronous, SDR
Access time3.4 ns
Memory size18Mbit
Memory formatSRAM
Case100-LQFP
Memory organization512K x 36

Product details

18 Mbit synchronous SRAM for high-throughput buffer applications

The CY7C1370DV25-167AXCT is a 18 Mbit synchronous SRAM from Infineon's NoBL (No Bus Latency) series, organized as 512K x 36 bits.

Supply rails and temperature grade

Operates from a 2.375 V to 2.625 V core supply — a narrow 250 mV window that demands a clean, low-noise rail.

Package and PCB footprint

Housed in a 100-LQFP (14x20 mm body) with the supplier device package designated as 100-TQFP. The 0.50 mm pitch requires a multi-layer board for fan-out; the exposed pad on the TQFP variant aids thermal conduction but is not present on the standard LQFP — verify the thermal pad land pattern against the mechanical drawing before layout.

Obsolete — sourcing via independent channels

No official successor or pin-compatible replacement is listed on the manufacturer's record. For new designs, a board spin to a current-generation synchronous SRAM with a similar package and interface is the migration path.

Frequently asked questions

What is the memory organization of CY7C1370DV25-167AXCT?

512K words by 36 bits — a total of 18 Mbit. The 36-bit word width suits systems needing parity or ECC bits alongside a 32-bit data bus.