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Infineon Technologies CY7C1370D-167AXIT — Memory (DRAM / SRAM / Flash / EEPROM)

CY7C1370D-167AXIT Infineon 18Mbit SRAM, 167 MHz, 100-TQFP

MPNCY7C1370D-167AXIT
Obsolete

Infineon Technologies NoBL™ series, CY7C1370D-167AXIT synchronous SRAM, 18Mbit, 512K x 36, 167 MHz, 3.4 ns access, 3.135V-3.6V, industrial -40°C to 85°C, 100-TQFP, Tape & Reel.

$35.8000Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C1370D-167AXIT specifications
ParameterValue
SeriesNoBL™
Memory typeVolatile
MountingSurface Mount
Supply voltage3.135V ~ 3.6V
Clock frequency167 MHz
Memory interfaceParallel
Operating temperature-40°C~85°C(TA)
PackageTape & Reel (TR)
TechnologySRAM - Synchronous, SDR
Access time3.4 ns
Memory size18Mbit
Memory formatSRAM
Case100-LQFP
Memory organization512K x 36

Product details

NoBL architecture and bus timing

The CY7C1370D-167AXIT: The NoBL (No Bus Latency) pipeline eliminates the turnaround cycle between read and write on the same port — the next access starts on the clock edge following the address, not after a wait state. At 167 MHz this saves one clock per transaction direction change, which matters when the memory is shared between a processor and a DMA engine. The parallel interface uses a common address and data bus, so the controller must match the timing to the SRAM's spec sheet limits.

Infineon lists the CY7C1370D-167AXIT as Obsolete.

Frequently asked questions

Where can I source the CY7C1370D-167AXIT?

The CY7C1370D-167AXIT is obsolete per Infineon. It is available through independent distribution — submit an RFQ for current availability and pricing. No stock-holding claim is made; each lot is confirmed at quote time.

What is the memory organization of the CY7C1370D-167AXIT?

The SRAM is organized as 512K words by 36 bits (18 Mbit total). The 36-bit word width matches a 32-bit data bus plus four parity or ECC bits without needing a second device.

Is the CY7C1370D-167AXIT suitable for new designs?

No — the part is obsolete. New designs should evaluate current-generation synchronous SRAMs from Infineon or alternate suppliers with compatible pinouts and timing.