18 Mbit synchronous SRAM, 133 MHz pipeline
The CY7C1370BV25-133AC is a 18 Mbit synchronous SRAM organized as 512K x 36. It operates at a 133 MHz clock frequency with a 4.2 ns access time — the access time sets the read-to-data-valid window at the bus interface, critical for timing closure in a pipelined memory controller. The memory interface is parallel, using SDR (single data rate) synchronous protocol. The 36-bit word width suits systems needing parity or ECC alongside a 32-bit data bus.
Core supply range is 2.375 V to 2.625 V — a tight 2.5 V nominal rail requiring a regulator with ±2.5% tolerance or better. Operating temperature is commercial grade: 0°C to 70°C (TA), suitable for indoor equipment but not extended or industrial environments.
100-TQFP package, 14x20 mm body
Housed in a 100-lead LQFP with the supplier device package listed as 100-TQFP (14x20). The 0.5 mm pitch demands careful fan-out on a four-layer board; the exposed paddle (if present on this variant) should be connected to ground plane for thermal relief. Surface-mount mounting.