Active synchronous SRAM for pipelined data buffering
The CY7C1367C-166AXCT is a 9 Mbit synchronous SRAM organized as 512K x 18 bits, clocked at 166 MHz with a 3.5 ns access time. It uses a single data rate (SDR) pipeline — each clock edge registers the address and control, and the data appears on the next rising edge, making it a natural fit for FPGA or ASIC memory interfaces that expect deterministic latency. The 18-bit word width (512K x 18) allows one parity bit per 16-bit data word, or a direct 18-bit bus for DSP/communication datapaths that carry control or tag bits alongside the data.
The supplier device package is 100-TQFP (14x20), which is the same footprint — the TQFP designation refers to the thinner profile variant of the LQFP. The 0.5 mm pitch requires a controlled-impedance PCB stack-up for the 166 MHz clock traces. It is not qualified for extended industrial or automotive environments.
Active lifecycle — sourcing posture
Sourced to order through independent distribution. Availability and current pricing confirmed at RFQ; no stock-holding claim is made here.