256K x 36 synchronous SRAM at 133 MHz
The CY7C1365CV33-133AXC: This is a 9 Mbit synchronous SRAM organized as 256K words of 36 bits. The 133 MHz clock rate and 6.5 ns access time place it in the pipeline-burst class — the address is latched on the rising clock edge, and the data appears after the programmed CAS latency. The 36-bit word width maps naturally to a 32-bit data bus plus parity or ECC nibble, common in network buffer and cache-tag applications.
Supply rails and temperature grade
Operates from a 3.14 V to 3.63 V core supply — a 3.3 V nominal rail with ±5 % tolerance covers the range without an extra regulator. The commercial temperature grade (0 °C to 70 °C) suits controlled indoor environments: telecom central offices, server racks, and ATE. The 100-TQFP package (14x20 mm body) requires a 0.5 mm pitch layout; the exposed pad on the underside should be connected to the PCB ground plane for thermal relief, though the datasheet's theta-JA figure governs the actual junction temperature under sustained 133 MHz switching.