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Infineon Technologies CY7C1362B-166AJC — Memory (DRAM / SRAM / Flash / EEPROM)

Cypress CY7C1362B-166AJC Synchronous SRAM, 9Mbit, 166 MHz

MPNCY7C1362B-166AJC
Obsolete

Cypress CY7C1362B-166AJC synchronous SRAM, 9Mbit (512K x 18), 166 MHz clock, 3.5 ns access time, parallel interface, 3.135 V to 3.6 V supply, 0°C to 70°C, 100-TQFP.

Infineon Technologies CY7C1362B-166AJC datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C1362B-166AJC specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Supply voltage3.135V ~ 3.6V
Clock frequency166 MHz
Memory interfaceParallel
Operating temperature0°C~70°C(TA)
PackageTray
TechnologySRAM - Synchronous, SDR
Access time3.5 ns
Memory size9Mbit
Memory formatSRAM
Case100-LQFP
Memory organization512K x 18

Product details

The 3.5 ns access means the SRAM can deliver data within one clock cycle at 166 MHz (6 ns period) with margin, so a properly timed controller sees zero wait-state reads in a pipelined bus. The 512K x 18 organization suits 18-bit DSP datapaths or networking lookup tables where the extra two bits carry parity or tag information.

3.3 V supply and commercial temperature — where it fits

It is not rated for industrial floors, automotive under-hood, or outdoor enclosures.

Obsolete — sourcing and replacement reality

Cypress lists the CY7C1362B-166AJC as Obsolete. For new designs, a synchronous SRAM in the same 100-TQFP footprint from another vendor — such as a 9 Mbit or 18 Mbit device with matching 512K x 18 or 1M x 18 organization — should be evaluated for timing compatibility.

Frequently asked questions

What is the replacement for CY7C1362B-166AJC?

No official replacement order code is recorded in the lifecycle data. For a pin-compatible alternative, evaluate other 9 Mbit or 18 Mbit synchronous SRAMs in the 100-TQFP package with a 512K x 18 or 1M x 18 organization and a 166 MHz clock rating. Verify timing (access time, setup/hold) against your controller before committing the BOM.

Is CY7C1362B-166AJC compatible with 3.3V logic?

Yes. No external level shifting is needed when connecting to a 3.3 V FPGA, ASIC, or processor memory controller.

What is the access time of CY7C1362B-166AJC?

The access time is 3.5 ns from clock rise. At a 166 MHz clock (6 ns period), this leaves 2.5 ns of margin for PCB trace delay and controller setup time, which is adequate for a single-board layout with short traces.