133 MHz synchronous SRAM for wide data-path designs
The Infineon CY7C1361C-133AXCT is a 9Mbit synchronous SDR SRAM organized as 256K x 36 bits, clocked at 133 MHz with a 6.5 ns access time. This part targets networking equipment, base stations, and DSP systems where a 36-bit wide data bus matches the processor or ASIC interface without external muxing.
Bus timing margin at 133 MHz
At 133 MHz the clock period is 7.5 ns, and the 6.5 ns access time leaves roughly 1 ns of setup margin before the next clock edge. That is tight — the board-level trace delay and clock skew need careful budgeting. The synchronous SDR pipeline eliminates the dead cycles of asynchronous SRAM on back-to-back reads, which matters for cache-line fills or packet buffer access patterns.
It suits indoor telecom racks, lab instrumentation, and office-environment equipment. Not rated for outdoor, automotive, or extended industrial use — if the ambient can push past 70°C, look at the industrial-grade sibling in the same family.
Listed as Active in the product lifecycle, so there is no imminent last-time-buy or end-of-life notice. The CY7C1361C-133AXCT is the Tape & Reel variant of the base CY7C1361C part; the tray-pack version (CY7C1361C-133AXC) shares identical silicon and timing.