133 MHz synchronous SRAM — what the clock and access time mean for the bus
The Infineon CY7C1361C-133AXC is a 9 Mbit synchronous SRAM organized 256K x 36, clocked at 133 MHz with a 6.5 ns access time. This is a pipelined synchronous part — the address is latched on the rising clock edge, and the data appears after the programmed CAS latency, so the bus can run back-to-back reads without dead cycles. The 36-bit word width maps directly to a 32-bit data bus plus parity or ECC lane, which saves an external mux in networking and DSP applications.
Package and footprint — 100-TQFP, surface-mount
Housed in a 100-TQFP (14x20 mm) package, the CY7C1361C-133AXC is a surface-mount device. The 100-LQFP footprint is common across the Cypress/Infineon synchronous SRAM families, so a layout done for a 100-pin QFP should carry over with a pinout check.
If you are stocking spares for an existing line, the active status also means the factory channel is still open — no need to hoard reels yet.