100 MHz synchronous SRAM — 9 Mbit in a 119-ball BGA
The CY7C1361C-100BGCT is a 9 Mbit synchronous SRAM organized as 256K x 36 bits, clocked at 100 MHz with an 8.5 ns access time. This is a parallel-interface, single-data-rate (SDR) SRAM — the 36-bit wide word suits high-throughput data buffers in networking, telecom, and test equipment where the bus width matches the processor or FPGA data path without multiplexing.
Infineon lists this part as Obsolete. The part is sourced through independent distribution — quantities are lot-specific and confirmed at RFQ. For a BOM that requires this exact footprint and timing, the 119-PBGA package and 100 MHz clock are fixed; a board spin would be needed for any alternative. Availability and pricing are confirmed per inquiry.
119-ball PBGA, 14x22 mm body. The 1.0 mm ball pitch demands a multi-layer PCB for fan-out — the inner balls route through via-in-pad or microvia layers. Supply decoupling should follow the recommended layout in the datasheet to keep the 3.135–3.6 V rail clean at 100 MHz. This limits the part to indoor, temperature-controlled environments — not suitable for extended industrial or automotive use without active cooling.