256K x 36 synchronous SRAM — 100 MHz, 8.5 ns access
The CY7C1361C-100AXC is a 9Mbit synchronous SRAM organized as 256K x 36, clocked at 100 MHz with an 8.5 ns access time. It uses a parallel interface and operates from a 3.135V to 3.6V supply. This is a single-data-rate (SDR) synchronous SRAM — the address is latched on the rising clock edge, and the 8.5 ns access time sets the window from clock edge to data valid. For a 100 MHz bus, that means the memory outputs settle well within the half-clock cycle, leaving margin for board trace delays.
100-TQFP package — rework and layout notes
The exposed pad on the underside is not present — this is a QFP, not a QFN, so thermal dissipation goes through the leads and the board copper. Rework is straightforward with hot air: the leads are visible for alignment, and the 0.5 mm pitch is forgiving enough for hand reflow with a fine tip. The 100-TQFP footprint is common across multiple SRAM vendors, so a layout designed for this part often accepts pin-compatible alternatives without a board spin.
It is suited for indoor equipment, networking gear, and industrial control cabinets where the ambient stays above freezing and below 70°C — not for extended outdoor or automotive use.