117 MHz synchronous SRAM — 256K x 36 wide bus
The CY7C1361A-117AJC is a 9 Mbit synchronous SRAM organized 256K words by 36 bits wide, clocked at 117 MHz with a 7 ns access time from clock edge. The 36-bit data bus makes it a natural fit for networking equipment that needs to buffer packet descriptors or forwarding tables in a single wide word — fewer parts than a 32-bit or 18-bit configuration, and the synchronous interface simplifies the controller timing. The commercial temperature grade (0 °C to 70 °C) limits deployment to indoor, temperature-controlled environments — no outdoor or industrial enclosure without active cooling.
Infineon lists this part as obsolete. This part is sourced to order against an RFQ. If you are qualifying a new design, the 117 MHz speed grade and 36-bit bus width narrow the parametric replacement search to other synchronous SRAMs in the same package, but a board spin is likely required.
Package and board-fit — 100-LQFP
Housed in a 100-lead LQFP (also specified as 100-TQFP, 14 mm x 20 mm body). The 0.5 mm pitch demands a 4-layer PCB for reliable fan-out of the 36 data lines plus address and control — two-layer boards will struggle with signal integrity at 117 MHz. The supplier device package code is 100-TQFP (14x20).