Obsolete — sourcing the BOM line through independent channels
The CY7C1360C-166AXIT: For a BOM line that depends on this exact part number, the supply path runs through independent distribution: quantities are lot-specific, and availability is confirmed at RFQ time. No pin-compatible drop-in replacement is documented here; a board spin or a parametric search across the same 256K x 36, 166 MHz class is the next step.
166 MHz clock, 3.5 ns access — the timing budget
This is a 9 Mbit synchronous SRAM organised 256K x 36, clocked at 166 MHz with a 3.5 ns access time from the clock edge. The 36-bit-wide data bus means a single chip delivers a full word without multiplexing — the controller reads or writes 36 bits every clock cycle at the rated frequency, provided the board layout keeps the parallel bus skew within the setup-and-hold window. The 3.5 ns access time is the time from the rising clock edge to valid data on the outputs. At 166 MHz the clock period is about 6 ns, so the access time consumes roughly 58% of the cycle — the remaining margin covers PCB trace delay, input capacitance, and the controller's own timing. This is a typical synchronous SRAM timing profile for networking and telecom line-card buffers where deterministic latency matters.
Industrial temperature, 100-TQFP, single 3.3 V rail
Packaged in a 100-lead LQFP (also listed as 100-TQFP, 14 x 20 mm body). The 0.5 mm pitch demands a controlled-impedance PCB stack-up for the 36-bit data bus at 166 MHz — a 2-layer board will struggle with signal integrity on the outer rows. The Tape & Reel (TR) suffix indicates reel packaging for automated pick-and-place.