Dual-port SRAM for shared-memory arbitration
The CY7C136-25JXCT: With a 25 ns access time and matching 25 ns write cycle, it suits shared-memory designs where two processors or controllers exchange data without bus arbitration overhead — common in telecom line cards, industrial controllers, and multiprocessor systems.
The 52-PLCC package (19.13 x 19.13 mm body) with J-lead contacts is a through-hole-reflow compatible footprint, suitable for socketed or soldered assembly on multilayer boards.
Available through independent distribution on a quoted-to-order basis. For existing BOM lines, verify the mating half and supply rail before committing.