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Infineon Technologies CY7C1357C-100AXC — Memory (DRAM / SRAM / Flash / EEPROM)

CY7C1357C-100AXC NoBL™ SRAM, 9Mbit, 100 MHz, 7.5 ns

MPNCY7C1357C-100AXC
Obsolete

Cypress NoBL™ synchronous SRAM, 9Mbit (512K x 18), 100 MHz clock, 7.5 ns access time, 3.3 V supply, 100-TQFP (14x20) package, commercial temperature range.

$9.1300Ref. price · indicative, final on quote
Infineon Technologies CY7C1357C-100AXC datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C1357C-100AXC specifications
ParameterValue
SeriesNoBL™
Memory typeVolatile
MountingSurface Mount
Supply voltage3.135V ~ 3.6V
Clock frequency100 MHz
Memory interfaceParallel
Operating temperature0°C~70°C(TA)
PackageTray
TechnologySRAM - Synchronous, SDR
Access time7.5 ns
Memory size9Mbit
Memory formatSRAM
Case100-LQFP
Memory organization512K x 18

Product details

What this NoBL™ SRAM does on the bus

The CY7C1357C-100AXC is a Cypress NoBL™ synchronous SRAM — 9 Mbit organized as 512K x 18, clocked at 100 MHz with a 7.5 ns access time. The NoBL™ (No Bus Latency) architecture eliminates the dead cycle normally required when switching from read to write or write to read, so back-to-back transactions run at full clock rate without a turnaround penalty. That matters in cache-tag, FIFO, and network-buffer applications where every cycle counts.

Package and supply — what to check on the board

No last-time-buy window remains open. Sourcing is limited to the surplus and broker channel, where stock is finite and prices reflect scarcity.

Frequently asked questions

Is CY7C1357C-100AXC obsolete?

Yes, the CY7C1357C-100AXC is listed as Obsolete. Cypress has discontinued production and no last-time-buy is active. Any remaining units are sourced through independent distribution against an RFQ.

What is the replacement for CY7C1357C-100AXC?

The closest pin-compatible alternative is the CY7C1357B variant (same 100-TQFP footprint and 512K x 18 organization), but verify timing and supply voltage compatibility against your design's timing budget before substituting.