9 Mbit synchronous SRAM with 3.5 ns access — the bus timing anchor
Rated for a 166 MHz clock with a 3.5 ns access time, it operates from a 2.375 V to 2.625 V supply and is housed in a 100-TQFP (14x20) package. This part targets high-throughput cache, FIFO, and network buffer applications where back-to-back transactions matter — the NoBL™ architecture lets the controller start a write on the cycle immediately following a read without an idle clock.
Infineon lists the CY7C1356CV25-166AXCT as Obsolete. No official successor part number appears in the lifecycle record. For a BOM line that still calls out this exact order code, supply now runs through independent distribution — new-old-stock or surplus inventory.
2.5 V supply, 100-TQFP — fit check for existing boards
The 2.375 V to 2.625 V supply range means this part runs on a 2.5 V rail, not the 3.3 V or 1.8 V common in newer SRAMs. The 100-TQFP (14x20) package is a surface-mount footprint with 0.5 mm pitch — verify that the board's existing decoupling and signal routing match the pinout of the NoBL™ synchronous interface.