166 MHz synchronous SRAM — the speed-density tradeoff
The CY7C1356C-166BGC is a 9 Mbit synchronous SRAM from Infineon's NoBL (No Bus Latency) family, organized as 512K x 18 bits. It clocks at 166 MHz with a 3.5 ns access time — the flow-through pipeline means the first read address appears on the data bus one cycle after the read command, then a new word every clock edge thereafter. For a cache line fill or a FIFO buffer running at that rate, the 3.5 ns access buys enough timing margin to avoid wait states in a typical 100-133 MHz bus.
Infineon has marked this part Obsolete.
Housed in a 119-ball PBGA (14x22 mm body), the 1.0 mm ball pitch is hand-solderable with a hot-air rework station and a stencil — not a breadboard-friendly part, but a rework lab can replace it with practice.