Infineon CY7C1355C-133AXCT, NoBL™ Synchronous SRAM, 9Mbit (256K x 36), 133 MHz clock, 6.5 ns access, 3.135V–3.6V supply, 100-TQFP (14x20 mm), commercial temperature 0°C to 70°C.
| Parameter | Value |
|---|---|
| Series | NoBL™ |
| Memory type | Volatile |
| Mounting | Surface Mount |
| Supply voltage | 3.135V ~ 3.6V |
| Clock frequency | 133 MHz |
| Memory interface | Parallel |
| Operating temperature | 0°C ~ 70°C (TA) |
| Package | Tape & Reel (TR) |
| Technology | SRAM - Synchronous, SDR |
| Access time | 6.5 ns |
| Memory size | 9Mbit |
| Memory format | SRAM |
| Case | 100-LQFP |
| Memory organization | 256K x 36 |
The Infineon CY7C1355C-133AXCT is a 9 Mbit synchronous SRAM from the NoBL (No Bus Latency) family, organized as 256K x 36 and clocked at 133 MHz with a 6.5 ns access time. The NoBL architecture eliminates the dead cycle normally required when switching between read and write operations on a common I/O bus, so back-to-back transactions sustain full throughput without wait states.
The CY7C1355C-133AXCT is manufactured as RoHS-compliant. The 'T' suffix in the ordering code designates the Tape & Reel package option, which is fully RoHS compliant per Infineon's standard product disclosure.
The CY7C1355C-133AXCT is an active part with no official replacement announced. The closest pin-compatible alternative within the same family is the earlier CY7C1355B-133AXC (tray) or CY7C1355B-133AXCT (Tape & Reel), which share the same footprint and function. For dual-sourcing, verify with Infineon's cross-reference tool for any second-source agreements; none are documented in the public record.
Yes. All I/O are 3.3 V compatible, so no level translation is needed when interfacing with other 3.3 V logic.