9 Mbit NoBL SRAM at 133 MHz — the bus-fit call
The Cypress CY7C1355C-133AXC is a 9 Mbit synchronous SRAM from the NoBL™ family, organized as 256K x 36, clocked at 133 MHz with a 6.5 ns access time. The NoBL pipeline eliminates dead cycles between reads and writes, which matters when back-to-back transactions eat into your bus margin. This part is built for networking gear, telecom line cards, and high-end test equipment where deterministic memory latency at speed is non-negotiable.
6.5 ns access — timing closure for a 133 MHz bus
The 6.5 ns access time is the window between clock edge and valid data on the outputs. At 133 MHz the clock period is about 7.5 ns, so that 6.5 ns leaves roughly 1 ns of setup margin before the next edge — tight but workable if your board's trace delay and clock skew are controlled. If you're running a 133 MHz memory bus, this part fits; if you need margin for a long flight-time backplane, a faster-access sibling (sub-6 ns) would be the safer call.
That means Cypress has stopped taking regular production orders, and the window for final purchases is closing. If you have an active design using this SRAM, now is the time to secure your lifetime buy or qualify a pin-compatible replacement. No official successor part is listed in the Cypress documentation, so a direct drop-in is not guaranteed.
100-TQFP — footprint and rework notes
It's a surface-mount, fine-pitch QFP — standard for synchronous SRAMs in this density tier.