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Infineon Technologies CY7C1353G-100AXCT — Memory (DRAM / SRAM / Flash / EEPROM)

Infineon CY7C1353G-100AXCT NoBL SRAM, 4.5 Mbit, 100 MHz

MPNCY7C1353G-100AXCT
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Infineon Technologies NoBL™ synchronous SRAM, CY7C1353G-100AXCT, 4.5 Mbit (256K x 18), 100 MHz clock, 8 ns access, 3.3 V, 100-TQFP, Tape & Reel.

$7.5687Ref. price · indicative, final on quote
Infineon Technologies CY7C1353G-100AXCT datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CY7C1353G-100AXCT specifications
ParameterValue
SeriesNoBL™
Memory typeVolatile
MountingSurface Mount
Supply voltage3.135V ~ 3.465V
Clock frequency100 MHz
Memory interfaceParallel
Operating temperature0°C ~ 70°C (TA)
PackageTape & Reel (TR)
TechnologySRAM - Synchronous, SDR
Access time8 ns
Memory size4.5Mbit
Memory formatSRAM
Case100-LQFP
Memory organization256K x 18

Product details

100 MHz synchronous SRAM — NoBL pipeline

The CY7C1353G-100AXCT is a 4.5 Mbit synchronous SRAM from Infineon's NoBL™ family, organized 256K x 18. It clocks at 100 MHz and delivers an 8 ns access time from clock edge to data valid — the NoBL pipeline eliminates dead cycles between back-to-back reads and writes, so the bus stays full on mixed transactions. The 18-bit word width (256K x 18) suits systems that need a parity or ECC bit per 16-bit data word without adding a second device.

Package and reflow profile

Housed in a 100-lead LQFP (supplier package 100-TQFP, 14x20 mm body). The 0.5 mm pitch QFP footprint is standard for fine-pitch placement; no exotic fan-out required on a 4-layer board. Tape & Reel (TR) packaging means the reel feeds directly into the pick-and-place feeder — no tray changeover.

Frequently asked questions

What does the NoBL series mean for bus efficiency?

NoBL (No Bus Latency) is Infineon's pipelined synchronous SRAM architecture. On back-to-back read-write sequences, the pipeline keeps the data bus active every clock cycle — there is no idle cycle for bus turnaround. For a 100 MHz bus, that saves 10 ns per transaction pair.