NoBL™ synchronous SRAM at 133 MHz — the pipeline that skips dead cycles
Unlike a standard synchronous SRAM that inserts a dead cycle when switching from read to write, NoBL™ allows back-to-back read-write transitions without a pipeline stall — every clock cycle carries a valid data transfer. This matters most in high-throughput datapath designs: network switch buffers, DSP coefficient tables, or test-equipment waveform memory where bus-turnaround latency directly eats into throughput margin.
133 MHz clock, 6.5 ns access — timing closure in a 100-pin TQFP
Rated for a 133 MHz clock with a 6.5 ns access time, this part delivers the setup-and-hold budget a 133 MHz synchronous interface demands. The 100-TQFP (14x20 mm) package keeps trace lengths short and signal integrity manageable; the 36-bit wide datapath (32 data plus four parity/byte-write bits) is a natural fit for 32-bit processors or DSPs that want a single-chip cache or look-up table without multiplexing.
Last-time-buy — the procurement window is open now
That means Infineon has announced end-of-life for this device, and there is a finite window to place final orders. If this SRAM is in your BOM — production, spares, or a legacy design refresh — the time to secure inventory is before the LTB deadline closes. Once the buy window passes, the only channel will be surplus and broker stock, with pricing and availability driven by remaining supply.
That is the commercial range — fine for office networking gear, bench instruments, telecom central-office equipment, or any climate-controlled indoor rack. If your system lives in a conditioned room, the commercial grade is a cost-appropriate fit.