NoBL synchronous SRAM for high-throughput cache and buffer applications
Typical applications include network packet buffers, cache memory for processors, and high-speed data acquisition systems where sustained throughput matters.
100 MHz clock and 8 ns access — timing closure for the bus
The 100 MHz clock frequency and 8 ns access time define the window for setup and hold on the data bus. With the NoBL pipeline, back-to-back reads and writes run at full clock rate without idle cycles, so the bus utilization hits the theoretical maximum for a single-data-rate synchronous SRAM. The 36-bit wide data path (128K x 36) matches 32-bit processor buses with parity or ECC bits, or two 18-bit devices in a wider memory array.
Package and footprint — 100-TQFP (14x20)
Housed in a 100-lead LQFP (also specified as 100-TQFP with 14x20 mm body), this is a surface-mount package with 0.5 mm pitch. The footprint is standard for high-density synchronous SRAMs of this generation. The supplier device package is 100-TQFP (14x20); verify the pin1 orientation against your layout — the LQFP and TQFP variants are the same mechanical outline.
Lifecycle and supply — active, no LTB risk
Infineon lists the CY7C1351G-100AXC as Active.