200 MHz synchronous SRAM in 100-LQFP
The CY7C1350G-200AXI is a 4.5 Mbit synchronous SRAM from Infineon's NoBL™ (No Bus Latency) family, organized 128K x 36 and clocked at 200 MHz. The 2.8 ns access time means the first read word appears on the data bus within three clock edges of the address — the pipeline depth is three cycles, so the latency is deterministic at 15 ns at 200 MHz. This part sits in the synchronous SRAM slot of a high-throughput memory map, typically a deep FIFO or cache buffer in networking or industrial control.
Infineon lists the CY7C1350G-200AXI as Obsolete.
The 100-TQFP package (14x20 mm body) has a 0.5 mm pitch that routes cleanly on a four-layer board with the VDDQ and VSS decoupling placed within 5 mm of each supply pin pair.