Skip to main content
Log in
Infineon Technologies CY7C1350G-200AXC — Memory (DRAM / SRAM / Flash / EEPROM)

CY7C1350G-200AXC NoBL SRAM, 4.5Mbit, 200 MHz, 2.8 ns

MPNCY7C1350G-200AXC
Active

Infineon NoBL™ CY7C1350G-200AXC synchronous SRAM, 4.5Mbit (128K x 36), 200 MHz clock, 2.8 ns access, parallel interface, 3.135V-3.6V supply, 0°C to 70°C, 100-TQFP.

$6.0500Ref. price · indicative, final on quote
Infineon Technologies CY7C1350G-200AXC datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CY7C1350G-200AXC specifications
ParameterValue
SeriesNoBL™
Memory typeVolatile
MountingSurface Mount
Supply voltage3.135V ~ 3.6V
Clock frequency200 MHz
Memory interfaceParallel
Operating temperature0°C ~ 70°C (TA)
PackageTray
TechnologySRAM - Synchronous, SDR
Access time2.8 ns
Memory size4.5Mbit
Memory formatSRAM
Case100-LQFP
Memory organization128K x 36

Product details

200 MHz synchronous SRAM with NoBL — what the 2.8 ns access buys you

The Infineon CY7C1350G-200AXC is a 4.5 Mbit synchronous SRAM organized 128K x 36, built on the NoBL (No Bus Latency) architecture. That means the memory can sustain back-to-back reads and writes on every clock cycle without inserting dead cycles for bus turnaround — a trait that matters when you are feeding a high-throughput datapath like a network processor or a DSP pipeline. The 200 MHz clock rate paired with a 2.8 ns access time gives the system architect a predictable timing budget: the address-to-data valid window is tight enough that you will want to close timing with the board's trace delay accounted for, but the part delivers the full 200 MT/s throughput when the pipeline is kept full.

128K x 36 — why the width matters

The 36-bit word width is deliberate: it matches a 32-bit data bus plus four parity bits (or ECC syndrome bits) without needing external byte-lane muxing. In a typical FPGA or ASIC cache application, you connect the 36-bit data bus directly to the core logic and use the extra two bits for in-line error detection. The 128K depth at that width means 4.5 Mbits total — enough for a moderate-size lookup table, a trace buffer, or a packet descriptor memory without spilling into a second device.

Supply and temperature — 3.3 V, commercial range only

The 100-pin TQFP (14x20 mm body) is a surface-mount package that reflows with standard lead-free profiles and is inspectable under a microscope, which the rework lab techs appreciate.

That said, the broader NoBL family has higher-density siblings (9 Mbit, 250 MHz) if the system outgrows this footprint — but those are different MPNs, not drop-in upgrades.

Board-level reality — 100-TQFP, 0.5 mm pitch

The 100-TQFP package has a 0.5 mm lead pitch. The PCB layout needs a soldermask-defined pad with a 0.25 mm to 0.30 mm pad width and a via-in-pad strategy if the decoupling caps sit on the back side. The supply pins are distributed around the periphery — you will want a 0.1 µF ceramic right at each VDDQ/VSS pair and a 4.7 µF bulk cap within 5 mm of the package. The 3.3 V core supply and the I/O supply share the same rail on this variant, so no separate VDDQ regulator is needed.

Frequently asked questions

What is the exact access time and clock speed of CY7C1350G-200AXC?

The access time is 2.8 ns and the maximum clock frequency is 200 MHz. These two numbers together define the timing budget: at 200 MHz the cycle time is 5 ns, and the 2.8 ns access means data is valid 2.8 ns after the clock edge that launches the address, leaving 2.2 ns for setup and hold on the receiving flip-flop.

Is CY7C1350G-200AXC a direct replacement for CY7C1350G-200AXI?

The CY7C1350G-200AXI is the industrial-temperature variant (typically -40°C to +85°C). The CY7C1350G-200AXC is the commercial-temperature variant (0°C to 70°C). They share the same 200 MHz speed grade, 2.8 ns access time, and 100-TQFP package, but the temperature range differs. If your application requires operation below 0°C, the AXI variant is the correct choice.

When sourcing CY7C1350G-200AXC, what is the closest functional alternative — CY7C1356C-250AXC?

The CY7C1356C-250AXC is a higher-density sibling (9 Mbit, 512K x 18) with a 250 MHz clock and the same 2.8 ns access time. It is not a pin-compatible drop-in — the organization and pinout differ (18-bit vs 36-bit word). It is a functional alternative if you need more memory depth at a higher clock rate and can adapt the board layout and bus width.