Synchronous SRAM for high-throughput datapaths
The Infineon CY7C1350G-133AXIT is a 4.5 Mbit synchronous SRAM from the NoBL (No Bus Latency) family, organized 128K x 36. It clocks at 133 MHz with a 4 ns access time, meaning the memory controller can start a new read or write on every clock edge without dead cycles between back-to-back transactions. The 36-bit word width suits it for processor local memory, networking packet buffers, or DSP coefficient storage where a wide datapath saves chip count.
No extended or military grade here, but the industrial rating handles most controlled environments and many harsh ones.
Housed in a 100-TQFP (14x20 mm) — a common, inspectable, and reworkable package. The 0.5 mm pitch fine-line QFP needs a decent soldering profile but is hand-solderable with practice.
Lifecycle — active, no obsolescence flag
Infineon lists the CY7C1350G-133AXIT as Active. No last-time-buy notice, no NRND designation.
