4.5 Mbit synchronous SRAM at 133 MHz
The CY7C1350G-133AXI: The 36-bit data bus means it can handle a 32-bit word plus parity or ECC bits in a single cycle — useful in networking and telecom line-card buffers where data integrity is checked alongside the payload.
Supply rails and temperature grade
No exposed thermal pad to worry about; decoupling caps go close to each supply pin pair on the board.
NoBL™ series — pipelined read/write
Part of Infineon's NoBL™ (No Bus Latency) family, this SRAM eliminates the dead cycle between read and write operations that older synchronous SRAMs require. On a 133 MHz bus, that one-cycle saving per transaction adds up — especially in cache-tag or FIFO applications where the bus direction flips every few clocks.