Dual-port SRAM for shared-memory handoff
The CY7C135-25JXC: 32 Kbit dual-port asynchronous SRAM organized as 4K x 8. Two independent ports allow separate bus masters to read or write the same memory location. Access time is 25 ns.
Access time is 25 ns. Write cycle time is also 25 ns.
Supplied in a 52-lead PLCC with J-leads, 19.13 x 19.13 mm body.
