128K x 36 synchronous SRAM at 250 MHz
The CY7C1347G-250AXCT is a 4.5 Mbit synchronous SRAM organized as 128K words of 36 bits each, clocked at 250 MHz with a 2.6 ns access time from the clock edge. The 36-bit word width maps directly to a 32-bit data bus plus 4 parity or ECC bits in a single chip — no need for a second device to cover the parity lane. The 100-TQFP (14x20 mm) package with 0.5 mm pitch requires a four-layer PCB for clean fan-out of the 36 data lines plus address and control signals.
The part is no longer supported for new designs and the last-time-buy window has closed. Available inventory is held in independent distribution and surplus channels. For a BOM that already carries this order code, the procurement path is through the spot market — not the factory.
Board-fit and supply integration
Decoupling with 0.1 µF and 10 µF ceramics per supply pin is standard for this clock rate. The 250 MHz clock input is LVTTL-compatible; the output drivers are also LVTTL with controlled impedance to reduce reflection on the data bus at this frequency.