Obsolete — 4.5 Mbit synchronous SRAM for existing designs
The CY7C1347F-133AC is officially classified as Obsolete by Infineon. This part is not recommended for new designs; it is available through independent surplus channels for legacy BOM support.
128K x 36 at 133 MHz — timing and footprint
This synchronous SRAM organises 4.5 Mbit as 128K words of 36 bits, accessed over a parallel interface at a 133 MHz clock rate. The 4 ns access time sets the read latency from address to data valid — a factor for timing closure in cache or buffer applications that share a bus with slower peripherals. The 100-TQFP package (14x20 mm body) uses a 0.5 mm pitch — a 4-layer PCB is typical for fan-out of the 100 pins.