128K x 36 synchronous SDR SRAM at 100 MHz — the wide-word cache line filler
The CY7C1345G-100AXCT is a 4.5 Mbit synchronous SDR SRAM organized 128K words by 36 bits. The 36-bit word width matches the data bus of many DSPs and network processors, letting a single chip supply a full cache line or MAC operand without byte-lane muxing. Rated for a 100 MHz clock, the part delivers pipelined read/write at that rate — the 8 ns access time is the first-word latency from address to data valid, not the cycle time. At 100 MHz the burst throughput is 400 MB/s on a 36-bit bus.
Supply and temperature — 3.3 V commercial, not industrial
The exposed pad on the TQFP improves thermal conduction to the ground plane.
Active lifecycle — no end-of-life watch needed
Infineon lists this part as Active. The base product number CY7C1345 covers the whole 128K x 36 synchronous SDR family; the G suffix indicates the 100 MHz speed grade, and the AXCT suffix specifies the 100-TQFP package on tape-and-reel.