133 MHz synchronous SRAM — 4 ns access, 128K x 32 organization
The CY7C1339G-133AXC: The synchronous pipeline delivers one word per clock cycle after the initial latency, making it suited for high-throughput cache or buffer applications where the parallel interface matches a 32-bit data bus.
The 100-TQFP (14x20 mm) package with 0.5 mm pitch requires a controlled impedance layout on the data and address lines to maintain signal integrity at 133 MHz.
Infineon has classified the CY7C1339G-133AXC as obsolete. No official successor or pin-compatible replacement is recorded from the manufacturer.