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Infineon Technologies CY7C1329-100AC — Memory (DRAM / SRAM / Flash / EEPROM)

Cypress CY7C1329-100AC SRAM, 2Mbit 100 MHz, 5.5 ns

MPNCY7C1329-100AC
Obsolete

Cypress CY7C1329-100AC, synchronous SRAM, 2Mbit (64K x 32), parallel interface, 100 MHz clock, 5.5 ns access time, 3.15V–3.6V supply, 100-LQFP, 0°C to 70°C.

Infineon Technologies CY7C1329-100AC datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C1329-100AC specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Supply voltage3.15V ~ 3.6V
Clock frequency100 MHz
Memory interfaceParallel
Operating temperature0°C ~ 70°C (TA)
PackageBag
TechnologySRAM - Synchronous, SDR
Access time5.5 ns
Memory size2Mbit
Memory formatSRAM
Case100-LQFP
Memory organization64K x 32

Product details

Not specified for industrial enclosures or outdoor cabinets.

The CY7C1329-100AC is marked obsolete by Cypress (now Infineon). No official successor part number is listed.

64K x 32 organization — what it buys you

The 64K x 32 organization means the memory array is 64K deep and 32 bits wide. Each read or write cycle transfers a full 32-bit word on the parallel bus, matching 32-bit processor data buses directly without byte-lane muxing. For a 32-bit RISC or DSP core, this SRAM connects straight to the data bus with no glue logic. The 2Mbit total density (64K words × 32 bits) is modest by today's standards — enough for a small packet buffer, a trace buffer, or a lookup table — but not enough for a frame buffer or large cache.

Frequently asked questions

Is CY7C1329-100AC obsolete?

Yes, the CY7C1329-100AC is obsolete. Cypress (now Infineon) has discontinued this part. No official replacement part number is listed. For existing BOMs, the part must be sourced through surplus or independent distribution channels.

What is the access time of CY7C1329-100AC?

The access time is 5.5 ns at a 100 MHz clock frequency. This means the SRAM can deliver data within one clock cycle at 100 MHz, leaving about 4.5 ns of bus margin for the controller.

CY7C1329-100AC vs CY7C1329-133AC differences?

The CY7C1329-133AC is the 133 MHz speed grade variant of the same 2Mbit synchronous SRAM. It has a faster access time (typically 4.5 ns) and a higher maximum clock frequency. Both use the same 100-LQFP package and 3.3V supply. The -133AC is also obsolete.

What is the pinout of CY7C1329-100AC?

The pinout is documented in the Cypress datasheet for the CY7C1329 family. The 100-LQFP package has 100 pins; the 64K x 32 organization uses 16 address pins (A0–A15), 32 data pins (DQ0–DQ31), plus control signals (CS#, WE#, OE#, ADV#, etc.). Refer to the datasheet for the full pin assignment.