Cypress (now Infineon) has ended production of this synchronous SDR SRAM. This is not a part you can design into a new build; it is a service-and-repair or last-time-buy fill for existing boards that already carry the footprint and timing budget.
133 MHz clock, 6.5 ns access — the timing budget
This synchronous SDR SRAM is clocked at 133 MHz with a 6.5 ns access time. The parallel interface means the address, data, and control signals share a common bus. This is a flow-through or pipelined synchronous architecture — the registered inputs latch on the clock rising edge, and the output registers update synchronously. No dead cycles on back-to-back reads if the pipeline is managed correctly.
2 Mbit organized 128K x 18 — fit check
The 2 Mbit density is organized as 128K words of 18 bits each.
Package and temperature — board-fit constraints
Supplied in a 100-TQFP (14x20 mm) package, surface-mount. Supply voltage range is 3.15V to 3.6V, nominally 3.3V. Core and I/O share the same rail. Decoupling should follow the datasheet recommendation for synchronous SRAM — typically one 0.1 µF ceramic per VDD pin pair, plus a bulk 10 µF on the board.
Sourcing this obsolete SRAM
Because this part is obsolete, the franchised distribution channel no longer stocks it. Availability is through independent distributors who hold verified new-old-stock or surplus inventory. If your BOM needs a production-quantity fill or a last-time-buy bridge, let us know the target quantity and date-code window.