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Infineon Technologies CY7C1320KV18-250BZXI — Memory (DRAM / SRAM / Flash / EEPROM)

Infineon CY7C1320KV18-250BZXI SRAM, 18Mbit, 250 MHz

MPNCY7C1320KV18-250BZXI
Active

Infineon CY7C1320KV18-250BZXI DDR II+ Synchronous SRAM, 18Mbit (512K x 36), 250 MHz clock, Parallel interface, 1.7V-1.9V supply, -40°C to +85°C, 165-FBGA (13x15) Tray.

$40.5200Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CY7C1320KV18-250BZXI specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Supply voltage1.7V ~ 1.9V
Clock frequency250 MHz
Memory interfaceParallel
Operating temperature-40°C~85°C(TA)
PackageTray
TechnologySRAM - Synchronous, DDR II
Memory size18Mbit
Memory formatSRAM
Case165-LBGA
Memory organization512K x 36

Product details

DDR II+ SRAM for high-throughput data paths

The Infineon CY7C1320KV18-250BZXI is a 18Mbit DDR II+ Synchronous SRAM organized as 512K x 36 bits, clocked at 250 MHz over a parallel interface. This is the part for network buffers, test equipment capture memory, or any pipeline that needs deterministic read-write cycles without refresh overhead.

250 MHz clock and 1.7V-1.9V core

The 250 MHz clock rate on a 512K x 36 organization means the part delivers a peak bandwidth around 2 GB/s on the data bus — the limiting factor in a real layout is the PCB trace length and termination, not the silicon. The 165-FBGA (13x15 mm) package puts the signal balls on a fine pitch — a four-layer board with buried vias is the practical minimum for routing the 36-bit data bus cleanly.

Infineon lists the CY7C1320KV18-250BZXI as Active.

Frequently asked questions

What is CY7C1320KV18-250BZXI's memory organization and clock speed?

It is organized as 512K x 36 bits (18Mbit total) and runs at a 250 MHz clock rate over a parallel interface. The DDR II+ architecture transfers data on both clock edges, effectively doubling the data rate relative to the clock.